1. Technical Field
The present invention generally relates to a method of forming electrical connections for a semiconductor device and, more particularly, to a method of forming electrical connections for a highly integrated semiconductor device.
2. Description of Related Art
Various processes are used in the fabrication of semiconductor devices in order to form the electrical connections between the device elements and the wirings for connecting the device to external devices. For example, multilevel metallization processes have been found to be useful for simplifying the fabrication of large scale integrated (LSI) devices. Such processes may be carried out to simultaneously form a wiring layer and a contact. One such multilevel metallization process is a so-called "dual damascene" process. A dual damascene process will be generally described with reference to FIGS. 1(a)-1(g). FIG. 1(a) shows a plurality of first level conductive structures 10 which are formed on an insulating film 7 which is formed on a silicon substrate 5. Conductive structures 10 may, for example, be formed of aluminum (Al), tungsten (W), tungsten silicide (WSi.sub.x), molybdenum silicide (MoSi.sub.x), titanium silicide (TiSi.sub.x), and the like. These conductive structures may, for example, be wirings, gate electrodes, bit lines, or lower level metallizations in a multi-metallization arrangement. As shown in FIG. 1(a), an insulating film 35 of silicon dioxide, for example, is formed on semiconductor substrate 5 and conductive structures 10. A first patterned resist film 40 is then formed as shown in FIG. 1(b) and a contact hole 45 which exposes one of the conductive structures 10 is formed by using an etching process such as reactive ion etching (RIE), for example, for etching insulating film 35 as shown in FIG. 1(c). A second patterned resist film 50 is then formed as shown in FIG. 1(d) and a wiring trench 55 is subsequently formed by an etching process such as RIE, for example, for etching insulating film 35 as shown in FIG. 1(e). Next, an aluminum film 60 is formed by sputtering as shown in FIG. 1(f). Aluminum film 60 is then polished by chemical mechanical polishing (CMP) as shown in FIG. 1(g). CMP is a combination of mechanical and chemical abrasion, and may be performed with an acidic or basic slurry. Material is removed from the wafer due to both the mechanical buffing and the action of the acid or base.
The damascene metallization process described above forms highly reliable wirings and contacts and provides good planarity of interlevel dielectric layers. As the integration density of semiconductor devices increases, the thickness of wirings generally decreases more slowly than the width of the wirings. Also, the thickness of contacts generally either does not change or decreases more slowly than the widths of the contacts as the integration density increases. As a result, the aspect ratio (i.e., depth/width) of wiring trenches and of contact or through holes formed in insulating films increases and high aspect ratio filling processes are required. In conventional metallization processes for forming wirings and contacts for semiconductor devices such as the process described above, an aluminum film is deposited using a sputtering method to fill the wiring trench/contact hole. The excess aluminum is then removed using CMP, for example. Aluminum is widely used for interconnects and wiring layers in semiconductor devices because of its low resistivity and ease of fabrication. However, the step coverage of an aluminum sputtering process is ineffective for filling without voids wiring trenches and/or contact holes having a high aspect ratios. Even using the long throw sputtering method for aluminum described in J. Vac. Sci. Tech., B13(4), July/August 1995 (pp. 1906-1909) or the reflow sputtering method for aluminum, only wiring trenches and/or contact holes with aspect ratios less than about 2 generally can be filled without voids. The presence of voids in aluminum wirings and contacts degrades the reliability of the wirings and contacts and adversely affects the performance of the semiconductor device.